1. Field of the Invention
The present invention generally relates to a leakage current control device of a semiconductor memory device, and more specifically, to a technology of effectively removing leakage current when a process defect is generated by gate residues.
2. Description of the Related Art
Generally, in most of DRAM planner processes using semiconductors a process defect caused by gate residues results in a bridge phenomenon which shorts neighboring metals.
Due to the bridge phenomenon between metals, an unnecessary current path is formed to increase power consumption of a memory, which degrades the performance of the product.
FIGS. 1 and 2 are diagrams illustrating a path of leakage current by the gate residue process defect in a conventional semiconductor memory device.
In the conventional semiconductor memory device, a word line WL and a bit line BL are connected to a resistor R and a capacitor C. While the semiconductor memory device is precharged, the word line WL transits to a ground voltage level, and the bit line BL is maintained at a core voltage/2 (bit line precharge voltage VBLP).
However, when the above-described state is maintained for a long time, a current path is formed from the bit line BL to the word line WL, so that unnecessary current is consumed. Moreover, it is difficult to solve the process defect by complementation on the process as a critical dimension of the semiconductor memory becomes more microscopic.
Specifically, a basic refresh operation is required to maintain data for the minimum power consumption at a standby mode of a low power consumption memory product. However, when leakage current is generated by a gate residue phenomenon at the standby mode of the low power consumption memory product, unnecessary current is consumed.